The invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". One of the materials used is silicon, which is used as either single crystal silicon or as polycrystalline silicon material, referred to as polysilicon or "poly" in this disclosure.
In the operation of certain semiconductor circuit devices, it is necessary to draw up a node of the sense amp to a high potential, for example, a potential approaching V.sub.CC. This node occurs on an array of a memory device such as a DRAM (dynamic random access memory). Other types of memory devices, such as static RAMs and video RAMs also may have such a circuit arrangement.
There are reasons that it is desirable that the node be pulled to a lower potential, such as V.sub.CC -V.sub.T (where V.sub.T is a threshold voltage of a transistor). If cell signal is large, it is desirable to very rapidly bring the potential of desirable to very rapidly bring the potential of the node to a high value. The biasing of this node enables the sense amp to sense a differential in signals between signal sources, such as between digit and digit* lines. If the node is at a low potential, the time for the sense amp to detect the differential in signal levels of the digit and digit* lines is greatly reduced. For the same reasons, it is advantageous to very rapidly bring the potential of the node to the high value.
Design objectives for the pull-up circuitry are: (1) to pull digit line (bit line) up as fast as possible, and (2) to keep the final potential less than (V.sub.CC -V.sub.TN), thereby lowering the equilibrate voltage and improving "1s" margin in the memory cell.
Thus far, the two conventional techniques, shown in FIGS. 1 and 2, have been widely used in the industry. Each of these implementations can only meet one of the two design objectives.
In one prior art technique, the memory array was strobed to a potential of V.sub.CC by gating a p-channel pull-up transistor.
The pumping of the node to V.sub.CC resulted in current consumption which would have been unnnecessary if the node were pumped to a lower value.
An alternate technique used an n-channel pull-up transistor or similar device to reduce the potential of the array after the pull up strobe to V.sub.CC -V.sub.T. This tended to slow the reaction time of the circuit because as the potential of the node approached V.sub.CC -V.sub.T, the change in potential would tend to slow, resulting in the potential of the node hyperbolically approaching that value.
If, as shown in FIG. 1, a prior art configuration with an n-channel transistor is used to connect the pull-up circuitry to V.sub.CC, the circuit suffers speed degradation, as shown in FIG. 3 (lower curve). Due to the source-follower configuration, as the gate of the pull up device rises, the source follows the gate. This keeps potential of the device to a minimum, and keeps the device "barely" on. This results in the source of the n-channel device being slowly pulled up to V.sub.CC -V.sub.TN.
The prior art p-channel case, shown in FIG. 2, suffers no speed loss because when the gate of the pull-up transistor goes low, the device turns on hard, pulling its drain up to V.sub.CC very quickly. The disadvantage is that the equilibrate voltage will be higher, causing a reduction in "1s" margin in the memory cell.
The inventive scheme combines the advantages of the above two configurations. It pulls the digit line towards V.sub.CC very quickly using a p-channel pull up to preserve the speed advantage and clamps the final level at V.sub.CC -V.sub.T, giving a lower equilibrate voltage, and ensuring good "1s" margin.
It would be desirable to have the potential of the node rise rapidly, as in the case of a p-channel transistor connection, but settle at a potential of V.sub.CC -V.sub.T.